82870P2P64H2 Datasheet, PDF (57/217 Pages) –

Register Description
R
Bits
Description
Hub Interface Master Abort (HMA)—R/WC. This bit is only visible from device 31.
0 = No hub interface master abort received.
12
1 = Intel® P64H2 generated a request on the hub interface and received a master abort
completion.
Note: Software clears this bit by writing a 1 to it.
PCI Target Abort (PTA)—R/WC.
0 = No PCI target abort received.
1 = P64H2 generated a cycle on PCI and received a target abort from a PCI target. It does not
11
set it for generating target aborts, because the only time this occurs is if there was a master
abort on the peer PCI agent or on the hub interface. In the case of peer PCI, the PRMA bit
will be set in the peer interface, and in the case of the hub interface, the HMA bit will have
been set.
Note: Software clears this bit by writing a 1 to it.
PCI Received Master Abort (PRMA)—R/WC.
0 = No master abort received.
10
1 = This bit indicates that the P64H2 generated a cycle on PCI and received a master abort.
Note: Software clears this bit by writing a 1 to it.
Single-bit ECC Address Error in from the Hub Interface (AEHS)—R/WC. This bit is only
visible from device 31.
0 = No single-bit ECC address error detected.
9
1 = Packet arrived on the hub interface that had a single-bit ECC error in the command phase
(address / header).
Note: Software clears this bit by writing a 1 to it.
Single-bit ECC Data error in from the Hub Interface (DEHS)—R/WC. This bit is only visible
from device 31.
0 = No single-bit ECC data error detected.
8
1 = P64H2 generated a cycle on the hub interface with a single-bit ECC error, or received a
packet on the hub interface with a single-bit ECC error.
Note: Software clears this bit by writing a 1 to it.
7
Reserved
Register Data Parity Error (RDPE)—R/WC.
0 = No register data parity error detected.
1 = Write with data parity error happens to any internal register (configuration or memory
6
mapped or I/O mapped) associated with this bridge. This includes the bridge registers, hot
plug registers, and APIC registers. This bit is not set if P64H2 is not the consumer of the
data and is simply forwarding the bad data across the bridge.
Note: Software clears this bit by writing a 1 to it.
Address parity error in from PCI (AEP)—R/WC.
0 = No address parity error detected.
5
1 = Address parity error was detected on PCI.
Note: Software clears this bit by writing a 1 to it.
Intel^® 82870P2 P64H2 Datasheet
57