82870P2P64H2 Datasheet, PDF (55/217 Pages) –

Register Description
R
3.2.28
PX_USTC—PCI-X Upstream Split Transaction Control
Register (D29,31: F0)
Offset:
58–5B
Attribute:
Default Value: 0000FFFFh Size:
R/W, RO
32 bits
This register controls the behavior of the P64H2’s buffers for forwarding Split Transactions from
the secondary bus to the hub interface.
Bits
Description
31:16
15:0
Split Transaction Limit (STL)—R/W. This field is not used by the Intel® P64H2 for modifying its
"commitment" level. The P64H2 internal launch algorithms keep buffers from being over
allocated. These read/write bits are provided for PCI-X diagnostic software.
Split Transaction Capacity (STC)—RO. The P64H2 essentially has infinite capacity, because
its launch algorithm keeps buffers from overrunning.
3.2.29
PX_DSTC—PCI-X Downstream Split Transaction Control
Register (D29,31: F0)
Offset:
5C–5Fh
Attribute:
Default Value: 0000FFFFh Size:
R/W, RO
32 bits
This register controls behavior of the P64H2 buffers for forwarding Split Transactions from the
hub interface to the secondary bus.
Bits
Description
31:16
15:0
Split Transaction Limit (STL)—R/W. This field is not used by the Intel® P64H2 for modifying its
"commitment" level. P64H2 internal launch algorithms keep buffers from being over allocated.
Split Transaction Capacity (STC)—RO. The P64H2 essentially has infinite capacity, because
its launch algorithm keeps buffers from overrunning.
Intel^® 82870P2 P64H2 Datasheet
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