82870P2P64H2 Datasheet, PDF (82/217 Pages) –

Register Description
R
3.3.1.24
XSR—PCI-X Status Register (Device 31)
Offset:
68–6Bh
Default Value: 0003xxF8h
Attribute:
Size:
RO
32 bits
Bits
31:21
20
19
18
17
16
15:8
7:3
2:0
Description
Reserved
Device Complexity. Hardwired to 0; indicates that this is a simple device.
Unexpected Split Completion. Hardwired to 0. This device will never see an unexpected split
completion, as it never generates any master cycles besides posted writes for MSI.
Split Completion Discarded. Hardwired to 0; this device does not support Split Completion.
133 MHz Capable. Hardwired to 1; indicates this device is 133 MHz capable.
64-bit Device. Hardwired to 1; indicates that this is a 64-bit device.
Bus Number. These bits indicate the bus number of the bus segment for this device. This value
will match the ‘secondary bus number’ field from the attached bridge. (Default = xxh)
Device Number. Hardwired to 1Fh; reflects the device number that has been hard-coded for the
device.
Function Number. Hardwired to 000b; reflects the function number that has been hard-coded for
the device.
3.3.1.25
ABAR—Alternate Base Register (Device 31)
Offset:
80–81h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
This register selects an alternate base register location for the memory working registers. The base
starts at FECX_YZ00h, where "X", "Y", and "Z" are written into bits 11:0. Bit 15 enables this
range. If enabled, decode of the memory space at FECX_YZ00h is performed, even if the memory
space enable bit in the PCI header is not set.
Bits
Description
15
14
13:12
11:8
7:4
3:0
Enable (EN): This bit enables decode range at FECXYZ00 to FECX_YZFF.
0 = Disable. (default)
1 = Enable.
SCI Enable (SCI EN): This bit enables SCI to be generated as opposed to interrupt. When
interrupts are unmasked and are to be sent, the value of this bit will be checked before sending
the interrupt on. If this bit is 0, a normal interrupt (pin or MSI) will be generated. If this bit is 1, an
SCI pin will be generated. The pin is active low.
0 = Disable. (default)
1 = Enable.
Reserved
Address Compare [19:16] (X): This field is compared against address bits 19:16.
Address Compare [15:12] (Y): This field is compared against address bits 15:12.
Address Compare [11:8] (Z): This field is compared against address bits 11:8.
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Intel^® 82870P2 P64H2 Datasheet