82870P2P64H2 Datasheet, PDF (161/217 Pages) –

Functional Description
R
Table 55. System Bus Delivery Address Format
Bit
Description
31:20
19:12
11:4
3
2
1:0
FEEh
Destination ID. This will be the same as bits [63:56] of the I/O Redirection Table entry for the
interrupt associated with this message.
Enhanced Destination ID. This will be the same as bits 55:48 of the I/O Redirection Table entry
for the interrupt associated with this message. If the system bus does not support 64-bit
addressing, these bits are reserved.
Redirection Hint. The processor host bridge (system bus) uses this bit to allow the interrupt
message to be redirected.
0 = The message will be delivered to the agent (processor) listed in bits 19:4.
1 = The message will be delivered to an agent with a lower interrupt priority
The Redirection Hint bit will be a 1 if bits 10:8 in the Delivery Mode field associated with
corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit
will be 0.
Destination Mode. This bit is used only the Redirection Hint bit is set to 1. If the Redirection Hint
bit and the Destination Mode bit are both set to 1, the logical destination mode is used, and the
redirection is limited only to those processors that are part of the logical group as based on the
logical ID.
00
Table 56. System Bus Delivery Data Format
Bit
Description
31:16
15
14
13:12
11
10:8
7:0
0000h
Trigger Mode. 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table
for that interrupt.
Delivery Status. 1 = Assert, 0 = Deassert. If using edge-triggered interrupts, then bit will always
be 1, since only the assertion is sent. If using level-triggered interrupts, then this bit indicates the
state of the interrupt input.
00
Destination Mode. 1 = Logical, 0 = Physical. Same as the corresponding bit in the Redirection
Table
Delivery Mode. This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
Vector. This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.
Intel^® 82870P2 P64H2 Datasheet
161