82870P2P64H2 Datasheet, PDF (40/217 Pages) –

Register Description
R
3.2.4
PD_STS—PCI Primary Device Status Register (D29,31: F0)
Offset:
06–07h
Default Value: 0030h
Attribute:
Size:
R/WC, RO
16 bits
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No address parity error, data parity error, or mulit-bit ECC error detected.
15 ^{1 = Intel® P64H2 detected an address parity, data parity, or multi-bit ECC error on the hub}
interface. This bit gets set even if the Parity Error Response (bit 6 of the PCI Primary Device
Command Register) is not set. Note that each bridge will set this bit, regardless of address.
Note: Software clears this bit by writing a 1 to it.
Signaled System Error (SSE)—R/WC.
0 = No SERR# is reported to the hub interface
14
1 = SERR# is reported to the hub interface via the DO_SERR special cycle.
Note: Software clears this bit by writing a 1 to it.
Received Master Abort (RMA)—R/WC.
0 = No Master Abort status received.
13
1 = P64H2 is acting as master on the hub interface and receives a completion packet with
master abort status.
Note: Software clears this bit by writing a 1 to it.
Received Target Abort (RTA)—R/WC.
0 = No target abort status received.
12
1 = P64H2 is acting as master on the hub interface and receives a completion packet with target
abort status.
Note: Software clears this bit by writing a 1 to it.
Signaled Target Abort (STA)—R/WC.
0 = No target abort status generated.
11
1 = P64H2 generates a completion packet with target abort status.
Note: Software clears this bit by writing a 1 to it.
10:9
DEVSEL# Timing (DVT)—RO. Hardwired to 00. These bits have no meaning on the hub
interface. Fast decode timing is reported.
Data Parity Error Detected (DPD)—R/WC.
0 = No data parity error or multi-bit ECC error detected.
8
1 = P64H2 receives a completion packet from the hub interface from a previous request, and
detects a parity or multi-bit ECC error, and the Parity Error Response bit in the PCI Primary
Device Command Register (offset 04h, bit 6) is set.
Note: Software clears this bit by writing a 1 to it.
7
Fast Back-to-Back Capable (FBC)—RO. Hardwired to 0. This bit has no meaning on the hub
interface.
40
Intel^® 82870P2 P64H2 Datasheet