82870P2P64H2 Datasheet, PDF (121/217 Pages) –

Functional Description
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4.1.9.2
4.1.9.3
4.1.9.4
4.1.9.5
Data Parity Errors
Unlike address parity errors, data parity errors are not considered as severe and transactions are
not aborted. The following sections describe the sequence of events when a data parity error is
detected for the following transactions:
• Configuration Write Transactions
• Read Transactions (inbound and outbound)
• Posted Write Transaction
Hub Interface Configuration Write Transactions
When the P64H2 detects a data parity error during a Type 0 configuration write transaction to one
of the P64H2 configuration spaces, the P64H2:
• Does not write the data to the configuration register if parity error response is enabled.
• Sets the Detected Parity Error bit (bit 15) in the PD_STS Register (offset 06–07h) of the
target (APIC, hot plug, bridge).
• Initiates the DO_SERR special cycle and sets the signaled system error bit (bit 14) in the
PD_STS Register, if the Parity Error Response Enable bit (bit 6) in the PD_CMD Register
(offset 04–05h) is set.
Read Transactions from Hub Interface Targeting PCI
When the P64H2 detects a read data parity error on the PCI bus from a hub interface initiated
read, it:
• Sets the Detected Parity Error bit (bit 15) in the Secondary Status Register (offset 1E–1Fh).
• Sets the Data Parity Detected bit (bit 8) in the Secondary Status Register (offset 1E–1Fh), if
the secondary interface parity error response bit (bit 0) is set in the Bridge Control Register
(offset 3E–3Fh).
• Forces bad parity or a multi-bit ECC error with the data back to the initiator on the hub
interface.
Read Transactions from PCI Targeting Hub Interface
When the P64H2 detects a data parity or multi-bit ECC error on a hub interface completion packet
from a previous memory read request on PCI, the P64H2:
• Sets the Detected Parity Error bit (bit 15) in the PD_STS Register (offset 06–07h).
• Sets the Data Parity Detected bit (bit 8) in the PD_STS Register (offset 06–07h) and generates
the DO_SERR special cycle, if the Primary Interface Parity Error Response bit (bit 6) is set in
the PD_CMD Register (offset 04–05h).
• Forwards the bad parity with the data back to PCI.
If a single bit ECC error is detected, it is corrected and none of the above occurs.
Intel^® 82870P2 P64H2 Datasheet
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