82870P2P64H2 Datasheet, PDF (195/217 Pages) –

Electrical Characteristics
R
5.2.2.1 PCI-X Clock Characteristics
Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in
a 3.3 V signaling environment except for voltage levels specified in Table 81.
The same spread-spectrum clocking techniques are allowed in PCI-X as for 66 MHz conventional
PCI. If a device includes a PLL, that PLL must track the input variations of spread-spectrum
clocking specified in Table 81.
Figure 22. PCI-X 3.3 V Clock Waveform
0.5 Vcc
0.4 Vcc
0.3 Vcc
T_high
T_cyc
0.6 Vcc
T_low
0.2 Vcc
0.4 Vcc, p-to-p
(minimum)
Time_PCIX-3_3VClock
Table 81. PCI-X Clock Timings (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0qC to 105qC)
PCI-X 133
PCI-X 66
Symbol
Parameter
Tcyc
Thigh
Tlow
—
PxPCLKO[6:0] cycle time
PxPCLKO[6:0] high time
PxPCLKO[6:0] low time
PxPCLKO[6:0] slew rate
Spread Spectrum Requirements
fmod
fspread
Modulation frequency
Frequency spread
Min
Max
Min Max Units Notes
7.5
20
15
30
ns
1, 3, 4
3
6
ns
3
6
ns
1.5
4
1.5
4
V/ns
2, 4
30
33
30
33
kHz
-1
0
-1
0
%
NOTES:
1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum
limits except while RSTIN# is asserted.
2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown
in Figure 23.
3. The minimum clock period must not be violated for any single clock cycle (i.e., accounting for all system
jitter).
4. All PCI-X 133 devices must also be capable of operating in PCI-X 66. All PCI-X devices must be
capable of operating in conventional PCI 33 mode and optionally are capable of conventional PCI 66
mode.
Intel^® 82870P2 P64H2 Datasheet
195