82870P2P64H2 Datasheet, PDF (153/217 Pages) –

Functional Description
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4.4.2 Memory Window Addressing
This section describes the memory windows that can be set up in the bridge. (Section outlines
memory cycles in the VGA range. The register bits listed below also modify the P64H2 response
to memory transactions:
• Memory-mapped I/O Base and Limit Registers
• Prefetchable Memory Base and Limit Registers
• Prefetchable Memory Base and Limit Upper 32 bits Register
• Memory Enable bit in the PCI Primary Device Command Register
• Master Enable bit in the PCI Primary Device Command Register
To enable outbound memory transactions, the Memory Space Enable bit (bit 1) in the PD_CMD
Register must be set (offset 04–05h). To enable inbound memory transactions, the Master Enable
bit (bit 2) in the PD_CMD Register must be set (offset 04–05h). The P64H2 will not prefetch data
from PCI devices. The P64H2 supports 64 bits of addressing (DAC cycles) on both interfaces.
4.4.2.1
Memory Base and Limit Address Registers
The Memory Base Address and Memory Limit Address Registers define an address range that the
P64H2 uses to determine when to forward memory commands. The P64H2 forwards a memory
transaction from the hub interface to PCI if the address falls within the range, and forwards it from
PCI to the hub interface (or the peer bridge) if the address is outside the range (provided that they
do not fall into the prefetchable memory range (see Section 4.4.2.2). This memory range supports
32-bit addressing only, (addresses 4 GB) and supports 1 MB granularity and alignment.
This range is defined by a 16-bit base address register at offset 20h in configuration space and a
16-bit limit address register at offset 22h. The top 12 bits of each of these registers correspond to
bits [31:20] of the memory address. The low 4 bits are hardwired to GND. The low 20 bits of the
base address are assumed to be all 0s, which results in a natural alignment to a 1 MB boundary.
The low 20 bits of the limit address are assumed to be all 1s, which results in an alignment to the
top of a 1 MB block.
Note: Setting the base to a value greater than that of the limit turns off the memory range.
4.4.2.2
Prefetchable Memory Base and Limit Address Registers,
Upper 32-bit Registers
The prefetchable memory base and address registers, along with their upper 32-bit counterparts,
define an additional address range that the P64H2 uses to forward accesses. The P64H2 forwards a
memory transaction from the hub interface to PCI if the address falls within the range, and
forwards transactions from PCI to the hub interface (or the peer bridge) if the address is outside
the range and do not fall into the regular memory range (see Section 4.4.2.1). This memory range
supports 64-bit addressing, and supports 1 MB granularity and alignment.
This lower 32-bits of the range are defined by a 16-bit base register at offset 24h in configuration
space and a 16-bit limit register at offset 28h. The top 12 bits of each of these registers correspond
to bits [31:20] of the memory address. The low 4 bits are hardwired to VCC, indicating 64-bit
address support. The low 20 bits of the base address are assumed to be all 0s, which results in a
Intel^® 82870P2 P64H2 Datasheet
153