82870P2P64H2 Datasheet, PDF (174/217 Pages) –

Functional Description
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4.8.3
I/OxAPIC System Assumptions
The I/OxAPICs in the P64H2 reside on the primary PCI bus. Therefore, it is conceivable that
devices on either bus may talk to either I/OxAPIC. However, special precautions must be made.
For devices that operate in “pin mode”, where a pin signals the interrupt, the interrupt pins that
reside on PCI bus A (PAIRQ[15:0]) must be routed to devices on PCI bus A or bridges that reside
behind PCI bus A. Similarly, interrupt pins that reside on PCI bus B (PBIRQ[15:0]) must be
routed to devices on PCI bus B or bridges that reside behind PCI bus B. This is because the
respective I/OxAPICs only perform buffer flushing for the PCI bus where interrupts are collected.
For devices in “MSI mode”, it is irrelevant how the interrupts are mapped. A device on PCI bus B
is allowed to perform an MSI to the I/OxAPIC on PCI bus A. This is because the MSI will
perform the buffer flush action on its respective bus.
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Intel^® 82870P2 P64H2 Datasheet