82870P2P64H2 Datasheet, PDF (48/217 Pages) –

Register Description
R
3.2.19
CAPP—Capabilities List Pointer Register (D29,31: F0)
Offset:
34h
Default Value: 50h
Attribute:
Size:
RO
8 bits
This register contains the pointer for the first entry in the capabilities list.
Bits
Description
7:0
Capabilities Pointer (PTR). This field indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
3.2.20
INTR—Interrupt Information Register (D29,31: F0)
Offset:
3C–3Dh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
This register contains information on interrupts on the bridge.
Bits
Description
15:08
07:00
Interrupt Pin (PIN). Bridges do not support the generation of interrupts.
Interrupt Line (LINE). The Intel® P64H2 Bridge does not generate interrupts, so this is reserved
as 00h.
3.2.21
BRIDGE_CNT—Bridge Control Register (D31: F0)
Offset:
3E–3Fh
Default Value: 0000h
Attribute:
Size:
R/W, R/WC
16 bits
This register provides extensions to the PCI Primary Device Command Register that are specific to
a bridge. The Bridge Control Register provides many of the same controls for the secondary
interface that are provided by the PCI Primary Device Command Register for the primary
interface. Some bits affect operation of both interfaces of the bridge.
Bits
Description
15:12
11
Reserved
Discard Timer SERR# Enable (DTSE)—R/W. This bit controls the generation of SERR# on the
primary interface in response to a timer discard on the secondary interface.
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard
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Intel^® 82870P2 P64H2 Datasheet