82870P2P64H2 Datasheet, PDF (113/217 Pages) –

Functional Description
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4.1.2 Transaction Types
Table 22 lists the PCI transactions supported by the P64H2. As a PCI master, the P64H2 has full
access to the 64-bit address space and can generate dual address cycles (DAC). As a target, the
P64H2 can accept dual address cycles up to the full 64-bit address space. The P64H2 supports the
linear increment address mode only for bursting memory transfers (indicated when the low 2
address bits are equal to 0). If either of these address bits is nonzero, the P64H2 disconnects the
transaction after the first data transfer.
The P64H2 decodes all PCI cycles in medium PxDEVSEL# timing.
Table 22. Intel^® P64H2 PCI Transactions
Type of Transaction
Intel^® P64H2 As
Master Target
Type of Transaction
Intel^® P64H2 As
Master Target
0000
0001
Interrupt
acknowledge
Special cycle
0010 I/O read
0011 I/O write
0100 Reserved¹
0101 Reserved¹
0110 Memory read
0111 Memory write
No
No
1000 Reserved¹
Yes
No
1001 Reserved¹
Yes
No
1010
Configuration
Read
Yes
No
1011
Configuration
Write
No
No
1100
Memory Read
Multiple
No
No
1101
Dual Address
Cycle
Yes
Yes
1110
Memory Read
Line
Yes
Yes
1111
Memory Write
and Invalidate
No
No
No
No
Yes
No
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
NOTES:
1. The P64H2 never initiates a PCI transaction with a reserved command code and ignores reserved
command codes as a target.
4.1.3
Detection of 64-bit Environment
The P64H2 drives PxREQ64# low during PCIRST# on each PCI interface to signal that the bus is
a 64-bit bus.
Intel^® 82870P2 P64H2 Datasheet
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