82870P2P64H2 Datasheet, PDF (162/217 Pages) –

Functional Description
R
4.6.3
4.6.4
Buffer Flushing
When the P64H2 receives an interrupt request, it will internally flush its buffers to DRAM. This is
necessary because the I/OxAPIC sits on the primary bus, but the data it affects was delivered on
the secondary bus, and this data may not have made it out of the P64H2 by the time the interrupt
arrives.
In serial mode this is not an issue, because the PCI device driver must do a read, which will force a
flush on the read return, but in front side bus mode, the PCI device driver will not do this read.
Therefore, the front side bus message that the APIC delivers must not go around the posted PCI
data in the internal buffer. This is accomplished by doing an internal flush.
In no circumstances will the P64H2 generate the APIC_FLUSH_REQ hub interface special cycle.
Boot Interrupt
The P64H2 contains a single interrupt output. This is necessary for systems that do not support the
APIC and for boot. The output of the P64H2 is the BT_INTR# pin.
162
Intel^® 82870P2 P64H2 Datasheet