S912XHY128F0VLM Datasheet, PDF (97/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.20 PIM Reserved Register
Address 0x0246
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-18. PIM Reserved Register
Access: User read¹
1
0
0
0
0
0
2.3.21 Port T Routing Register (PTTRR)
Address 0x0247
7
R
PTTRR7
W
6
PTTRR6
5
PTTRR5
4
PTTRR4
3
PTTRR3
2
PTTRR2
Routing
Option
IOC0_7
IOC0_5
IOC0_4
IOC0_6
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Anytime}
Write: Anytime
Figure 2-19. Port T Routing Register (PTTRR)
Access: User read¹
1
0
PTTRR1
PTTRR0
IOC1_7
0
IOC1_6
0
This register configures the re-routing of TIM0/1 channels on alternative pins on Port R/T.
Table 2-16. Port T Routing Register Field Descriptions
Field
[7:6] Port T data direction—
PTTRR This register controls the routing of IOC0_7.
Description
5
PTTRR
00 IOC0_7 routed to PT7
01 IOC0_7 routed to PR1
10 IOC0_7 routed to PV6
11 IOC0_7 routed to PT7(reserved)
Port T data direction—
This register controls the routing of IOC0_5.
0 IOC0_5 routed to PT5
1 IOC0_5 routed to PV2
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
97