S912XHY128F0VLM Datasheet, PDF (136/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.78 Port AD Interrupt Flag Register (PIF1AD)
Address 0x028D
R
W
Reset
7
PIF1AD7
0
1 _{Read: Anytime.}
Write: Anytime.
6
PIF1AD6
5
PIF1AD5
4
PIF1AD4
3
PIF1AD3
2
PIF1AD2
0
0
0
0
0
Figure 2-75. Port F Interrupt Flag Register (PIF1AD)
Access: User read/write¹
1
0
PIF1AD1 PIF1AD0
0
0
Table 2-63. PIF1AD Register Field Descriptions
Field
Description
7-0
PIF1AD
Port AD interrupt flag—
Each flag is set by an active edge on the associated input pin. To clear this flag, write logic level 1 to the
corresponding bit in the PIF1AD register. Writing a 0 has no effect. ¹
1 Active falling edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
1 _{In order to enable the Key Wakeup function, need to set the ATDIENL first.}
2.3.79 Port R Interrupt Enable Register (PIER)
Read: Anytime.
Address 0x028E
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
0
PIER4
PIER3
PIER2
0
0
0
0
0
Figure 2-76. Port R Interrupt Enable Register (PIER)
Access: User read/write¹
1
0
PIER1
PIER0
0
0
Field
4-0
PIER
Table 2-64. PIER Register Field Descriptions
Description
Port R interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port R.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
MC9S12XHY-Family Reference Manual, Rev. 1.01
136
Freescale Semiconductor