S912XHY128F0VLM Datasheet, PDF (249/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Highest
Lowest
S12X Debug (S12XDBGV3) Module
Table 6-39. Trigger Priorities
TRIG
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Match3 (force or tag hit)
Trigger immediately to final state (begin or mid aligned tracing enabled)
Trigger immediately to state 0 (end aligned or no tracing enabled)
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
6.4.4 State Sequence Control
ARM = 0
State 0
(Disarmed)
ARM = 1
ARM = 0
State1
State2
ARM = 0
Session Complete
(Disarm)
Final State
State3
Figure 6-22. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register,
then state1 of the state sequencer is entered. Further transitions between the states are then controlled by
the state control registers and depend upon a selected trigger mode condition being met. From Final State
the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is
not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current
state.
Alternatively by setting the TRIG bit in DBGSC1, the state machine can be triggered to state0 or Final
State depending on tracing alignment.
Independent of the state sequencer, each comparator channel can be individually configured to generate an
immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.
Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer
transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a
channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This
is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state
sequencer enters state0 and the debug module is disarmed.
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
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