S912XHY128F0VLM Datasheet, PDF (173/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Memory Mapping Control (S12XMMCV4)
Expansion of the BDM Local Address Map
PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the
global address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
3.4.2.2 Global Addresses Based on the Global Page
CPU Global Addresses Based on the Global Page
The seven global page index bits allow access to the full 8MB address map that can be accessed with 23
address bits. This provides an alternative way to access all of the various pages of FLASH, RAM and Data
FLASH.
The GPAGE Register is used only when the CPU is executing a global instruction (see Section 3.3.2.2,
“Global Page Index Register (GPAGE)). The generated global address is the result of concatenation of the
CPU local address [15:0] with the GPAGE register [22:16] (see Figure 3-7).
BDM Global Addresses Based on the Global Page
The seven BDMGPR Global Page index bits allow access to the full 8MB address map that can be accessed
with 23 address bits. This provides an alternative way to access all of the various pages of FLASH, RAM
and Data FLASH.
The BDM global page index register (BDMGPR) is used only in the case the CPU is executing a firmware
command which uses a global instruction (like GLDD, GSTD) or by a BDM hardware command (like
WRITE_W, WRITE_BYTE, READ_W, READ_BYTE). See the BDM Block Guide for further details.
The generated global address is a result of concatenation of the BDM local address with the BDMGPR
register [22:16] in the case of a hardware command or concatenation of the CPU local address and the
BDMGPR register [22:16] in the case of a firmware command (see Figure 3-18).
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
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