S912XHY128F0VLM Datasheet, PDF (532/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Timer Module (TIM16B8CV2) Block Description
To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0
respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the
OC7M register must also be cleared.
To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in
the OC7M register must also be cleared. The settings for these bits can be seen in Table 16-10
Table 16-10. The OC7 and OCx event priority
OC7M7=0
OC7Mx=1
TC7=TCx
TC7>TCx
OC7Mx=0
TC7=TCx
TC7>TCx
IOCx=OC7Dx IOCx=OC7Dx
IOC7=OM7/O +OMx/OLx
L7
IOC7=OM7/O
L7
IOCx=OMx/OLx
IOC7=OM7/OL7
OC7M7=1
OC7Mx=1
TC7=TCx
TC7>TCx
OC7Mx=0
TC7=TCx
TC7>TCx
IOCx=OC7Dx IOCx=OC7Dx
IOC7=OC7D7 +OMx/OLx
IOC7=OC7D7
IOCx=OMx/OLx
IOC7=OC7D7
Note: in Table 16-10, the IOS7 and IOSx should be set to 1
IOSx is the register TIOS bit x,
OC7Mx is the register OC7M bit x,
TCx is timer Input Capture/Output Compare register,
IOCx is channel x,
OMx/OLx is the register TCTL1/TCTL2,
OC7Dx is the register OC7D bit x.
IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value.
16.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
Module Base + 0x000A
R
W
Reset
7
EDG7B
0
6
EDG7A
5
EDG6B
4
EDG6A
3
EDG5B
2
EDG5A
0
0
0
0
0
Figure 16-16. Timer Control Register 3 (TCTL3)
1
EDG4B
0
0
EDG4A
0
Module Base + 0x000B
R
W
Reset
7
EDG3B
0
6
EDG3A
5
EDG2B
4
EDG2A
3
EDG1B
2
EDG1A
0
0
0
0
0
Figure 16-17. Timer Control Register 4 (TCTL4)
MC9S12XHY-Family Reference Manual, Rev. 1.01
532
1
EDG0B
0
0
EDG0A
0
Freescale Semiconductor