S912XHY128F0VLM Datasheet, PDF (166/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Memory Mapping Control (S12XMMCV4)
Write: Anytime
These eight index bits are used to page 16KB blocks into the Flash page window located in the local (CPU
or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-12). This supports
accessing up to 4MB of Flash (in the Global map) within the 64KB Local map. The PPAGE register is
effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions..
Global Address [22:0]
1 Bit21
Bit14 Bit13
Bit0
PPAGE Register [7:0]
Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 3-12. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
Table 3-7. PPAGE Field Descriptions
Field
7–0
PIX[7:0]
Description
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and
0xFFFF out of reset.
The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF.
3.3.2.6 RAM Page Index Register (RPAGE)
Address: 0x0016
R
W
Reset
7
RP7
1
6
RP6
1
5
RP5
1
4
RP4
1
3
RP3
1
2
RP2
1
1
RP1
0
0
RP0
1
Figure 3-13. RAM Page Index Register (RPAGE)
MC9S12XHY-Family Reference Manual, Rev. 1.01
166
Freescale Semiconductor