S912XHY128F0VLM Datasheet, PDF (150/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.96 Port V Routing Register (PTVRR)
Address 0x029F
7
6
5
4
3
2
R
0
0
0
0
PTVRR3 PTVRR2
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-93. Port V Routing Register (PTVRR)
Access: User read¹
1
0
0
0
0
0
This register configures the re-routing of TIM1 channels on alternative pins on Port M/V.
Table 2-79. Port V Routing Register Field Descriptions
Field
2
Port V Routing Register—
PTVRR This register controls the routing of IOC1_2
Description
3
PTVRR
0 IOC1_2 routed to PV4
1 IOC1_2 routed to PM2
Port V Routing Register—
This register controls the routing of IOC1_3.
0 IOC1_3 routed to PV6
1 IOC1_3 routed to PM3
2.4 Functional Description
2.4.1 General
Each pin except BKGD can act as general purpose I/O. In addition each pin can act as an output or input
of a peripheral module.
2.4.2 Registers
A set of configuration registers is common to all ports with exception of the ATD port (Table 2-80). All
registers can be written at any time, however a specific configuration might not become active.
For example selecting a pull-up device: This device does not become active while the port is used as a
push-pull output.
MC9S12XHY-Family Reference Manual, Rev. 1.01
150
Freescale Semiconductor