S912XHY128F0VLM Datasheet, PDF (547/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 17
Liquid Crystal Display (LCD40F4BV2) Block Description
Revision History
Table 17-1. LCD40F4BV2 Revision History
Version
Number
Revision
Date
Effective
Date
Author
Description of Changes
01.00
01.08
01.09
02.01
26-Jul-00
27-Mar-08
25-Apr-08
29-Jul-09
initial LCD module spec
New specification for 9S12HY family based on 9S12H family specification
Update for 9S12HY defining last registers as unimplemented
add pseudo stop feature
17.1 Introduction
The LCD40F4BV2 driver module has 40 frontplane drivers and 4 backplane drivers so that a maximum of
160 LCD segments are controllable. Each segment is controlled by a corresponding bit in the LCD RAM.
Four multiplex modes (1/1, 1/2, 1/3, 1/4 duty), and three bias (1/1, 1/2, 1/3) methods are available. The V₀
voltage is the lowest level of the output waveform and V₃ becomes the highest level. All frontplane and
backplane pins can be multiplexed with other port functions.
The LCD40F4BV2 driver system consists of five major sub-modules:
• Timing and Control – consists of registers and control logic for frame clock generation, bias
voltage level select, frame duty select, backplane select, and frontplane select/enable to produce
the required frame frequency and voltage waveforms.
• LCD RAM – contains the data to be displayed on the LCD. Data can be read from or written to the
display RAM at any time.
• Frontplane Drivers – consists of 40 frontplane drivers.
• Backplane Drivers – consists of 4 backplane drivers.
• Voltage Generator – Based on voltage applied to VLCD, it generates the voltage levels for the
timing and control logic to produce the frontplane and backplane waveforms.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
547