S912XHY128F0VLM Datasheet, PDF (255/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Field
5
CRW
S12X Debug (S12XDBGV3) Module
Table 6-42. CXINF Field Descriptions (continued)
Description
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing CPU12X activity in Detail Mode.
0 Write Access
1 Read Access
6.4.5.4 Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read using either the background debug module (BDM) module
or the CPU12X provided the S12XDBG module is not armed, is configured for tracing and the system not
secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer
can only be unlocked for reading by an aligned word write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid 64-bit lines can be determined. DBGCNT will not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to
DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be
easily restarted from the oldest data entry.
The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1
and 0 of Table 6-40. The bytes containing invalid information (shaded in Table 6-40) are also read out.
Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of
the RAM pointer will occur.
6.4.5.5 Trace Buffer Reset State
The Trace Buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace
session information from immediately before the reset occurred can be read out. The DBGCNT bits are
not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is
indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking
the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session.
Generally debugging occurrences of system resets is best handled using mid or end trigger alignment since
the reset may occur before the trace trigger, which in the begin trigger alignment case means no
information would be stored in the trace buffer.
NOTE
An external pin RESET that occurs simultaneous to a trace buffer entry can,
in very seldom cases, lead to either that entry being corrupted or the first
entry of the session being corrupted. In such cases the other contents of the
trace buffer still contain valid tracing information. The case occurs when the
reset assertion coincides with the trace buffer entry clock edge.
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
255