S912XHY128F0VLM Datasheet, PDF (177/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Memory Mapping Control (S12XMMCV4)
3.4.3 Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM )
with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping
operations. All internal resources are connected to specific target buses (see Figure 3-20).
MMC
BDM
S12X1
Address Decoder & Priority
CPU
S12X0
DBG
Target Bus Controller
XBUS0
Data FLASH PGMFLASH
RAM
Peripherals
Figure 3-20. MMC Block Diagram
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
177