S912XHY128F0VLM Datasheet, PDF(206/802 Page) Freescale Semiconductor, Inc – S12 Microcontrollers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

S912XHY128F0VLM Datasheet, PDF (206/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

◁

Background Debug Module (S12XBDMV2)

5.4.1 Security

If the user resets into special single chip mode with the system secured, a secured mode BDM ï¬rmware

lookup table is brought into the map overlapping a portion of the standard BDM ï¬rmware lookup table.

The secure BDM ï¬rmware veriï¬es that the on-chip non-volatile memory (e.g. EEPROM and Flash

EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program

jumps to the start of the standard BDM ï¬rmware and the secured mode BDM ï¬rmware is turned off and

all BDM commands are allowed. If the non-volatile memory does not verify as erased, the BDM ï¬rmware

sets the ENBDM bit, without asserting UNSEC, and the ï¬rmware enters a loop. This causes the BDM

hardware commands to become enabled, but does not enable the ï¬rmware commands. This allows the

BDM hardware to be used to erase the non-volatile memory.

BDM operation is not possible in any other mode than special single chip mode when the device is secured.

The device can be unsecured via BDM serial interface in special single chip mode only. For more

information regarding security, please see the S12X_9SEC Block Guide.

5.4.2 Enabling and Activating BDM

The system must be in active BDM to execute standard BDM ï¬rmware commands. BDM can be activated

only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)

register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire

interface, using a hardware command such as WRITE_BD_BYTE.

After being enabled, BDM is activated by one of the following3:

â¢ Hardware BACKGROUND command

â¢ CPU BGND instruction

â¢ External instruction tagging mechanism4

â¢ Breakpoint force or tag mechanism4

When BDM is activated, the CPU ï¬nishes executing the current instruction and then begins executing the

ï¬rmware in the standard BDM ï¬rmware lookup table. When BDM is activated by a breakpoint, the type

of breakpoint used determines if BDM becomes active before or after execution of the next instruction.

NOTE

If an attempt is made to activate BDM before being enabled, the CPU

resumes normal instruction execution after a brief delay. If BDM is not

enabled, any hardware BACKGROUND commands issued are ignored by

the BDM and the CPU is not delayed.

In active BDM, the BDM registers and standard BDM ï¬rmware lookup table are mapped to addresses

0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses

these registers which are readable anytime by the BDM. However, these registers are not readable by user

programs.

3. BDM is enabled and active immediately out of special single-chip reset.

4. This method is provided by the S12X_DBG module.

MC9S12XHY-Family Reference Manual, Rev. 1.01

206

Freescale Semiconductor

▷