S912XHY128F0VLM Datasheet, PDF (226/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12X Debug (S12XDBGV3) Module
6.1.5 Block Diagram
TAGHITS
SECURE
S12XCPU BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MATCH0
MATCH1
MATCH2
MATCH3
TAGS
BREAKPOINT REQUESTS
S12XCPU
TRIGGER
TAG &
TRIGGER
CONTROL
LOGIC
STATE
STATE
STATE SEQUENCER
TRACE
CONTROL
TRIGGER
READ TRACE DATA (DBG READ DATA BUS)
Figure 6-1. Debug Module Block Diagram
6.2 External Signal Description
The S12XDBG sub-module features no external signals.
6.3 Memory Map and Registers
TRACE BUFFER
6.3.1 Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 6-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address
0x0020
0x0021
Name
R
DBGC1
W
R
DBGSR
W
Bit 7
ARM
TBF
6
0
TRIG
0
5
reserved
0
4
BDM
0
3
2
DBGBRK reserved
0
SSF2
0x0022
0x0023
R
DBGTCR
reserved TSOURCE
W
R
0
0
DBGC2
W
TRANGE
0
0
TRCMOD
CDCM
Figure 6-2. Quick Reference to S12XDBG Registers
1
Bit 0
COMRV
SSF1
SSF0
TALIGN
ABCM
MC9S12XHY-Family Reference Manual, Rev. 1.01
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