S912XHY128F0VLM Datasheet, PDF (110/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.36 Port M Polarity Select Register (PPSM)
Address 0x0255
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
PPSM3
PPSM2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-33. Port M Polarity Select Register (PPSM)
Access: User read/write¹
1
0
PPSM1
PPSM0
0
0
Table 2-29. PPST Register Field Descriptions
Field
3-0
PPSM
Description
Port M pull device select—Configure pull device polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
1 A pull-down device is selected
0 A pull-up device is selected
2.3.37 Port MWired-Or Mode Register (WOMM)
Address 0x0256
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-34. Port MWired-Or Mode Register
Access: User read¹
1
0
WOMM1 WOMM0
1
1
Table 2-30. WOMM Register Field Descriptions
Field
Description
1-0
WOMM
Port M wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
MC9S12XHY-Family Reference Manual, Rev. 1.01
110
Freescale Semiconductor