S912XHY128F0VLM Datasheet, PDF (139/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

2.3.83 Port U Data Direction Register (DDRU)
Port Integration Module (S12XHYPIMV1)
Address 0x0292
R
W
Reset
7
DDRU7
0
1 _{Read: Anytime.}
Write: Anytime.
6
DDRU6
5
DDRU5
4
DDRU4
3
DDRU3
2
DDRU2
0
0
0
0
0
Figure 2-80. Port U Data Direction Register (DDRU)
Access: User read/write¹
1
0
DDRU1
DDRU0
0
0
Table 2-68. DDRU Register Field Descriptions
Field
Description
7,5,3,1 Port U data direction—
DDRU If enabled the Motor driver PWM output it will force the I/O state to be output.
6,4,2,0
DDRU
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port U data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
Else if corresponding TIM0 output compare channel is enabled, it will be force as output
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTU or PTIU registers, when changing the
DDRU register.
2.3.84 PIM Reserved Registers
Address 0x0293
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-81. PIM Reserved Registers
Access: User read¹
1
0
0
0
0
0
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
139