S912XHY128F0VLM Datasheet, PDF (65/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 2
Port Integration Module (S12XHYPIMV1)
Revision History
Version
Number
0.01
0.02
Revision
Date
18 May
2009
8 Jun
2009
Effective
Date
0.03
9 Jun
2009
0.04
10 Jun
2009
0.05
23 Jun
2009
0.06
25 Jun
2009
0.07
29 Jul
2009
0.08
30 Jul
2009
0.09
27 OCT
2009
Author
Initial Version
Description of Changes
add pin routing of IOC0[7:4] to PV(Table 2-1)
add port M to pin functions in Table 2-1
fix typo
remove WOMM in register map Table 2-2./2-74
update link in register map Table 2-2./2-74
PERM reserved bit reset value is 0 in 2.3.18/2-96
update by steven’s review on v0.01
update by team review based on Ver0.04
update PWM re-route PTRRH&PTRRL
Change IOC re-route on PM to PU/PV. SCI re-route on PM to PH
update by team review
add SSD pin functions in pinmap
update wire-or options on port M
fix, add IOC1_1 IOC1_0 to Table 2-1., “Pin Functions and Priorities
fix, add IOC0_7 to 2.3.89, “Port V Data Register (PTV)
Fix wong figure name in Section 2.3.54, “Port H Routing Register
(PTHRR)
remove reduded drive strength descript in Section 2.1.2, “Features
update ranget for Section 2.3.9, “PIM Reserved Register
fix Table 2-2, add PTTRR{7:4]
fix table/figure name Table 2-58,Table 2-59,Figure 2-70,Figure 2-71
fix table/figure name Table 2-62,Figure 2-75
update WOMM[1:0] at Figure 2-34,Figure 2-2, Figure 2-80
update Figure 2-80,reduced drive,Routing,Wire-Or
fix Table 2-38, un-hidePMM5:4] routing
fix Table 2-95, port name for glitch
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
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