S912XHY128F0VLM Datasheet, PDF (108/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Field
3-0
PTIM
Table 2-26. PTIM Register Field Descriptions
Description
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.33 Port M Data Direction Register (DDRM)
Address 0x0252
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
DDRM3
DDRM2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-30. Port M Data Direction Register (DDRM)
Access: User read/write¹
1
0
DDRM1
DDRM0
0
0
Table 2-27. DDRM Register Field Descriptions
Field
Description
3-2
DDRM
Port M data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding output compare channel is enabled, it will be forced as output.
Else if the corresponding PWM7-6 are enabled, the corresponding I/O state will be forced to output. In this case the
data direction bit will not change.
1-0
DDRM
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding output compare channel is enabled, it will be forced as output.
Else if the corresponding PWM5-4 are enabled, the corresponding I/O state will be forced to output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTM or PTIM registers, when changing the
DDRT register.
MC9S12XHY-Family Reference Manual, Rev. 1.01
108
Freescale Semiconductor