S912XHY128F0VLM Datasheet, PDF(313/802 Page) Freescale Semiconductor, Inc – S12 Microcontrollers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

S912XHY128F0VLM Datasheet, PDF (313/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

◁

Voltage Regulator (S12VREGL3V3V1)

9.4.11.1 Low-Voltage Interrupt (LVI)

In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the

status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID. An

interrupt, indicated by ï¬ag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable

bit LVIE = 1.

NOTE

On entering the Reduced Power Mode, the LVIF is not cleared by the

VREG_3V3.

9.4.11.2 HTI - High Temperature Interrupt

In FPM VREG monitors the die temperature TDIE. Whenever TDIE exceeds level THTIA the status bit

HTDS is set to 1. Vice versa, HTDS is reset to 0 when TDIE get below level THTID. An interrupt, indicated

by ï¬ag HTIF=1, is triggered by any change of the status bit HTDS if interrupt enable bit HTIE=1.

NOTE

On entering the Reduced Power Mode the HTIF is not cleared by the VREG.

9.4.11.3 Autonomous Periodical Interrupt (API)

As soon as the conï¬gured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated

by ï¬ag APIF = 1, is triggered if interrupt enable bit APIE = 1.

MC9S12XHY-Family Reference Manual Rev. 1.01

Freescale Semiconductor

313

▷