S912XHY128F0VLM Datasheet, PDF (84/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Register
Name
Bit 7
6
5
4
0x0297 R
0
0
0
0
PTURR _W
0x0298 R
PTV _W
PTV7
PTV6
PTV5
PTV4
0x0299 R
PTIV _W
PTIV7
PTIV6
PTIV5
PTIV4
0x029A R
DDRV _W ^DDRV7
DDRV6
DDRV5
DDRV4
0x029B R
0
0
0
0
Reserved _W
0x029C R
PERV _W ^PERV7
PERV6
PERV5
PERV4
0x0294D R
PPSV
PPSV7
PPSV6
PPSV5
PPSV4
0x029E R
SRRV _W ^SRRV7
SRRV6
SRRV5
SRRV4
0x029F R
0
0
0
0
PTVRR _W
= Unimplemented or Reserved
3
2
PTURR3 PTURR2
PTV3
PTIV3
PTV2
PTIV2
DDRV3
0
DDRV2
0
PERV3
PERV2
PPSV3
PPSV2
SRRV3
SRRV2
PTVRR3 PTVRR2
1
0
PTV1
PTIV1
DDRV1
0
PERV1
PPSV1
SRRV1
0
Bit 0
0
PTV0
PTIV0
DDRV0
0
PERV0
PPSV0
SRRV0
0
2.3.2 Register Descriptions
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR),
output level (IO), pull enable (PE), pull select (PS) on the pin function and pull device activity.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
MC9S12XHY-Family Reference Manual, Rev. 1.01
84
Freescale Semiconductor