S912XHY128F0VLM Datasheet, PDF (130/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.67 Port R Data Direction Register (DDRR)
Address 0x0282
R
W
Reset
7
DDRR7
0
1 _{Read: Anytime.}
Write: Anytime.
6
DDRR6
5
DDRR5
4
DDRR4
3
DDRR3
2
DDRR2
0
0
0
0
0
Figure 2-64. Port R Data Direction Register (DDRR)
Access: User read/write¹
1
0
DDRR1
DDRR0
0
0
Table 2-54. DDRR Register Field Descriptions
Field
7
DDRR
Description
Port R data direction—
This register controls the data direction of pin 7.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
6
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 6.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
5
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 5.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
4
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 4.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
3-2
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 3-2.This register configures pin as either input or output.
If TIM1/ are routing to the PR and TIM1 output compare functions are enabled, it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12XHY-Family Reference Manual, Rev. 1.01
130
Freescale Semiconductor