S912XHY128F0VLM Datasheet, PDF (63/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Revision History
Version
Number
Rev0.07
Revision
Date
Jul-29-2009
Rev0.08
Rev0.09
Jul-30-2009
OCT-30-2009
Rev0.10 Nov-11-2009
Rev0.11
Rev0.12
Jun-03-2010
Nov-16-2010
Device Overview MC9S12XHY-Family
Author
Daniel
Daniel
Daniel
Daniel
Daniel
Daniel
Description of Changes
add SSD pin defines
update typo
update PIM
update Table 1-2., “Device Register Memory Map, 0x0400-0x07FF
is reserved
update Section Figure 1-2., “MC9S12XHY-Family Global Memory
Map
update Section Table 1-5., “Port Availability by Package Option for
sum of power pins
update Section Table 1-5., “Port Availability by Package
Option,VDD/VSS2
fix Section 1.7.4.4, “VDDF / VSS1 — NVM Power Pins
fix Section 1.7.4.5, “VDDA / VSSA — Power Supply Pins for ATD
and Voltage Regulator
update Section Figure 1-5., “Clock Connections, add lcd clock, add
SSD IIC MC
fix Section Table 1-2., “Device Register Memory Map, SSD name
update Table 1-1,bus speed is 40MHz
update 1.8 System Clock Description, for lcd clock
update Table 1-7., “Pin-Out Summary, reset state of pin RESET
fix 1.12, “COP Configuration, FOPT address is 0x7_FF0E
Fix typo of Table 1-2./1-23, size of Moudle INT is 16, 0x130~ is 16
update Table 1-1./1-14,all parts has 2x MSCAN and SCI
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
63