S912XHY128F0VLM Datasheet, PDF (755/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Electrical Characteristics
In Figure A-10 the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS
(Output)
SCK
(CPOL = 0)
(Output)
SCK
(CPOL = 1)
(Output)
MISO
(Input)
1
2
4
4
5
6
MSB IN2
9
MOSI
(Output)
Port Data
Master MSB OUT2
12
12
Bit MSB-1. . . 1
11
Bit MSB-1. . . 1
13
3
13
LSB IN
Master LSB OUT
Port Data
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
Figure A-10. SPI Master Timing (CPHA = 1)
In Table A-26 the timing characteristics for master mode are listed.
Table A-26. SPI Master Mode Timing Characteristics
Num C
Characteristic
Sym
bol
Min
Typ
Max
Unit
1
D SCK frequency
1
D SCK period
MIN(16, f_bus/2)¹
f_sck
f_bus/2048
— MIN(10,f_bus/2) ² MHZ
MIN(0.8,f_bus/2)³
MAX(62.5, 2*t_bus)¹
t_sck MAX(100, 2*t_bus)²
—
2048 ∗ t_bus
ns
MAX(1250, 2*t_bus)³
2
D Enable lead time
t_lead
—
1/2
—
t_sck
3
D Enable lag time
t_lag
—
1/2
—
t_sck
4
D Clock (SCK) high or low time
t_wsck
—
1/2
—
t_sck
5
D Data setup time (inputs)
t_su
8
—
—
ns
6
D Data hold time (inputs)
t_hi
8
—
—
ns
9
D Data valid after SCK edge
t_vsck
—
—
29
ns
10 D Data valid after SS fall (CPHA = 0)
t_vss
—
—
15
ns
11 D Data hold time (outputs)
t_ho
20
—
—
ns
12 D Rise and fall time inputs
t_rfi
—
—
8
ns
13 D Rise and fall time outputs
t_rfo
—
—
8
ns
1^{SPI on non-motor pad ports (Port S or Por t H)}
2^{SPI on Port V with slew rate control disable. All the SPI pins slew rate control should be disabled.}
3^{SPI on Port V with slew rate control enabled. All the SPI pins slew rate control should be enabled.}
4. MIN(16, f_bus/2) means select minimum frequency value from 16MHZ and f_bus/2MHZ. same for the other MIN(X,Y)
5. MAX(62.5, 2*t_bus) means select the maximum period value from 62.5ns and 2*t_bus ns. same for the other MAX(X,Y)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
755