S912XHY128F0VLM Datasheet, PDF (137/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

2.3.80 Port R Interrupt Flag Register (PIFR)
Port Integration Module (S12XHYPIMV1)
Address 0x028F
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
0
PIFR4
PIFR3
PIFR2
0
0
0
0
0
Figure 2-77. Port R Interrupt Flag Register (PIFR)
Access: User read/write¹
1
0
PIFR1
PIFR0
0
0
Field
4-0
PIFR
Table 2-65. PIFR Register Field Descriptions
Description
Port R interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSR register. To clear this flag, write logic level 1 to the corresponding bit in the PIFR register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
2.3.81 Port U Data Register (PTU)
Address 0x0290
R
W
Altern.
Function
Reset
7
PTU7
—
M1C1P
M1SINP
0
1 _{Read: Anytime.}
Write: Anytime.
6
PTU6
5
PTU5
4
PTU4
3
PTU3
2
PTU2
IOC0_3
—
IOC0_2
—
IOC0_1
M1C1M
M1C0P
M1C0M
M0C1P
M0C1M
M1SINM
0
M1COSP M1COSM M0SINP
M0SINM
0
0
0
0
Figure 2-78. Port U Data Register (PTU)
Access: User read/write¹
1
0
PTU1
PTU0
—
M0C0P
M0COSP
0
IOC0_0
M0C0M
M0COSM
0
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
137