S912XHY128F0VLM Datasheet, PDF (131/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-54. DDRR Register Field Descriptions (continued)
Field
1
DDRR
Description
Port R data direction—
This register controls the data direction of pin 1.This register configures pin as either input or output.
If TIM0 are routing to the PR and TIM0 output compare functions are enabled, it will force as output.
Else If TX of CAN1 is routing to PR and CA1 is enabled, it will force as output.
0
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 3-0.This register configures pin as either input or output.
If TIM1/TIM0 are routing to the PR and TIM1/TIM0 output compare functions are enabled, it will force as output.
Else If RX of CAN1 is routing to PR and CA1 is enabled, it will force as input.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
2.3.68 PIM Reserved Registers
Address 0x0283
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-65. PIM Reserved Register
Access: User read/write¹
1
0
0
0
0
0
2.3.69 Port R Pull Device Enable Register (PERR)
Address 0x0284
R
W
Reset
7
PERR7
1
6
PERR6
5
PERR5
4
PERR4
3
PERR3
2
PERR2
1
1
1
1
1
Figure 2-66. Port R Pull Device Enable Register (PERR)
Access: User read/write¹
1
0
PERR1
PERR0
1
1
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
131