S912XHY128F0VLM Datasheet, PDF (134/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.74 Port T Interrupt Flag Register (PIFT)
Address 0x0289
R
W
Reset
7
PIFT7
0
1 _{Read: Anytime.}
Write: Anytime.
6
PIFT6
5
PIFT5
4
PIFT4
3
PIFT3
2
PIFT2
0
0
0
0
0
Figure 2-71. Port TInterrupt Flag Register (PIFT)
Access: User read/write¹
1
0
PIFT1
PIFT0
0
0
Table 2-59. PIFT Register Field Descriptions
Field
Description
6-5
PIFT
Port T interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPST register. To clear this flag, write logic level 1 to the corresponding bit in the PIFS register. Writing
a 0 has no effect.¹
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
1 _{In order to enable the key wakup function, need to disable the LCD FP function first}
2.3.75 Port S Interrupt Enable Register (PIES)
Read: Anytime.
Address 0x028A
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
PIES6
PIES5
PIES3
PIES2
0
0
0
0
0
Figure 2-72. Port S Interrupt Enable Register (PIES)
Access: User read/write¹
1
0
0
0
0
0
Table 2-60. PIES Register Field Descriptions
Field
Description
6-5 3-2
PIES
Port S interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port S.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
MC9S12XHY-Family Reference Manual, Rev. 1.01
134
Freescale Semiconductor