S912XHY128F0VLM Datasheet, PDF (20/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12XHY-Family
1.3.18 On-Chip Voltage Regulator (VREG)
• Linear voltage regulator with bandgap reference
• Low-voltage detect (LVD) with low-voltage interrupt (LVI)
• Power-on reset (POR) circuit
• Low-voltage reset (LVR)
1.3.19 Background Debug (BDM)
• Background debug module (BDM) with single-wire interface
• Non-intrusive memory access commands
• Supports in-circuit programming of on-chip nonvolatile memory
1.3.20 Debugger (DBG)
• Three comparators A, B, C, and D to monitor CPU buses
• Trace buffer with depth of 64 entries
• Comparator A and C compares full address bus and 16-bit data bus with mask register
• Three modes: simple address/data match, inside address range, or outside address range
1.3.21 SSD
• Programmable Full Step State
• Programmable Integration polarity
• Blanking (recirculation) state
• 16-bit Integration Accumulator register
• 16-Bit Modulus Down Counter with interrupt
• Multiplex two stepper motors
1.3.22 INT (interrupt module)
• Seven levels of nested interrupts
• Flexible assignment of interrupt sources to each interrupt level.
• External non-maskable high priority interrupt (XIRQ)
• The following inputs can act as Wake-up Interrupts
— IRQ and non-maskable XIRQ
— CAN receive pins
— SCI receive pins
— Depending on the package option up to 25 pins on ports R, S, T and AD, configurable as rising
or falling edge sensitive
•
MC9S12XHY-Family Reference Manual, Rev. 1.01
20
Freescale Semiconductor