S912XHY128F0VLM Datasheet, PDF (69/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Port Pin Name
H PH[7:4]
PH[3]
Pin Function
& Priority¹
FP[26:23]
GPIO
FP[22]
I/O
Description
O LCD frontplane segment driver output
I/O General purpose
O LCD frontplane segment driver output
Pin Function
after Reset
GPIO
PH[2]
PH[1]
PH[0]
SS
GPIO
FP[21]
SCK
ECLK
GPIO
FP[20]
TXD1
MOSI
GPIO
FP[19]
RXD1
I/O SS of SPI, mappable through software
I/O General purpose
O LCD frontplane segment driver output
I/O SCK of SPI, mappable through software
O Free-running clock at bus clock rate or programmable
down-scaled bus clock
I/O General purpose
O LCD frontplane segment driver output
I/O Serial Communication Interface(SCI1) transmit pin
I/O MOSI of SPI, mappable through software
I/O General purpose
O LCD frontplane segment driver output
I/O Serial Communication Interface(SCI1) receive pin
MISO
GPIO
I/O MISO of SPI, mappable through software
I/O General purpose
M PM[3:2]
PM[1]
PM[0]
PP[7:0]
P
IOC1[3:2]
PWM[7:6]
GPIO
TXD1
IOC0[3]
PWM[5]
GPIO
RXD1
IOC0[2]
PWM[4]
GPIO
FP[7:0]
PWM[7:0]
GPIO
I/O TIM1 channel [3:2], mappable through software
I/O Pulse Width Modulator channel 7 - 6
I/O General purpose
O TXD of SCI1
I/O TIM0 channel [3], mappable through software
I/O Pulse Width Modulator channel 5
I/O General purpose
I RXD of SCI1
I/O TIM0 channel [2], mappable through software
I/O Pulse Width Modulator channel 4
I/O General purpose
O LCD frontplane segment driver output
I/O Pulse Width Modulator channel 7 - 0
I/O General purpose
GPIO
GPIO
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
69