S912XHY128F0VLM Datasheet, PDF (85/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-3. Pin Configuration Summary
DDR
IO
RDR¹
PE
PS²
IE³
Function
0
x
x
0
x
0
x
x
1
0
0
x
x
1
1
0
x
x
0
0
0
x
x
0
1
0
x
x
1
0
0
x
x
1
1
1
0
0
x
x
1
1
0
x
x
1
0
1
x
x
1
1
1
x
x
1
0
0
x
0
1
1
0
x
1
1
0
1
x
0
1
1
1
x
1
1 _{not Applicable only on MC9S12XHY}
2 _{Always “1” on Port A, B, and always “0” on AD.}
3 _{Applicable only on Port T, S, R,M and AD.}
0
Input
0
Input
0
Input
1
Input
1
Input
1
Input
1
Input
0
Output, full drive to 0
0
Output, full drive to 1
0
Output, reduced drive to 0
0
Output, reduced drive to 1
1
Output, full drive to 0
1
Output, full drive to 1
1
Output, reduced drive to 0
1
Output, reduced drive to 1
Pull Device
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Interrupt
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
NOTE
Figure of port data registers also display the alternative functions if
applicable on the related pin as defined in Table 2-1. Names in brackets
denote the availability of the function when using a specific routing option.
NOTE
Figures of module routing registers also display the module instance or
module channel associated with the related routing bit.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
85