S912XHY128F0VLM Datasheet, PDF (103/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

2.3.26
Port Integration Module (S12XHYPIMV1)
Port S Pull Device Enable Register (PERS)
Address 0x024C
R
W
Reset
7
PERS7
1
1 _{Read: Anytime.}
Write: Anytime.
6
PERS6
5
PERS5
4
PERS4
3
PERS3
2
PERS2
1
1
1
1
1
Figure 2-24. Port S Pull Device Enable Register (PERS)
Access: User read/write¹
1
0
PERS1
PERS0
1
1
Table 2-20. PERS Register Field Descriptions
Field
7-0
PERS
Description
Port S pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.27 Port S Polarity Select Register (PPSS)
Address 0x024D
R
W
Reset
7
PPSS7
0
1 _{Read: Anytime.}
Write: Anytime.
6
PPSS6
5
PPSS5
4
PPSS4
3
PPSS3
2
PPSS2
0
0
0
0
0
Figure 2-25. Port S Polarity Select Register (PPSS)
Access: User read/write¹
1
0
PPSS1
PPSS0
0
0
Table 2-21. PPSS Register Field Descriptions
Field
7-0
PPSS
Description
Port S pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A rising edge on the associated Port S pin sets the associated flag bit in the PIFS register. A pull-down device is
connected to the associated pin, if enabled and if the pin is used as input.
0 A falling edge on the associated Port S pin sets the associated flag bit in the PIFS register. A pull-up device is
connected to the associated pin, if enabled and if the pin is used as input.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
103