S912XHY128F0VLM Datasheet, PDF (159/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Memory Mapping Control (S12XMMCV4)
3.1.3 S12X Memory Mapping
The S12X architecture implements a number of memory mapping schemes including
• a CPU 8MB global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
• a BDM 8MB global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
• a (CPU or BDM) 64KB local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64KB visible at any instant can be considered
as the local map accessed by the 16-bit (CPU or BDM) address.
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
3.1.4 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the MMC.
3.1.4.1 Power Saving Modes
• Run mode
MMC is functional during normal run mode.
• Wait mode
MMC is functional during wait mode.
• Stop mode
MMC is inactive during stop mode.
3.1.4.2 Functional Modes
• Single chip modes
In normal and special single chip mode the internal memory is used.
3.1.5 Block Diagram
Figure 3-1 shows a block diagram of the MMC.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
159