S912XHY128F0VLM Datasheet, PDF (519/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 16
Timer Module (TIM16B8CV2) Block Description
Table 16-1. Revision History
Revision
Number
Revision Date
Sections
Affected
Description of Changes
V02.04
V02.05
V02.06
V02.07
1 Jul 2008
9 Jul 2009
26 Aug 2009
04 May 2010
16.3.2.12/16-53 - Revised flag clearing procedure, whereby TEN bit must be set when clearing
5
flags.
16.3.2.13/16-53
5
16.3.2.16/16-53
8
16.4.2/16-543
16.4.3/16-543
16.3.2.12/16-53 - Revised flag clearing procedure, whereby TEN or PAEN bit must be set
5
when clearing flags.
16.3.2.13/16-53 - Add fomula to describe prescaler
5
16.3.2.15/16-53
7
16.3.2.16/16-53
8
16.3.2.19/16-54
0
16.4.2/16-543
16.4.3/16-543
16.1.2/16-520 - Correct typo: TSCR ->TSCR1
16.3.2.15/16-53 - Correct reference: Figure 1-25 -> Figure 1-31
7
- Add description, “a counter overflow when TTOV[7] is set”, to be the
16.3.2.2/16-526 condition of channel 7 override event.
16.3.2.3/16-527 - Phrase the description of OC7M to make it more explicit
16.3.2.4/16-528
16.4.3/16-543
16.3.2.8/16-531 - Add Table 16-10
16.3.2.11/16-53 - in TCRE bit description part,add Note
4
- Add Figure 16-31
16.4.3/16-543
16.1 Introduction
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable
prescaler.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
519