S912XHY128F0VLM Datasheet, PDF (245/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12X Debug (S12XDBGV3) Module
when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite
number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address
when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an
opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is verified at a given address, this
address may not still contain that data value when a subsequent match occurs.
Comparators C and D can also be used to select an address range to trace from. This is determined by the
TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 6-9. If the TRANGE
bits select a range definition using comparator D, then comparator D is configured for trace range
definition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range
definition using comparator C, then comparator C is configured for trace range definition and cannot be
used for address bus comparisons.
Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see
Section 6.3.2.4”). Comparator priority rules are described in the trigger priority section (Section 6.4.3.4”).
6.4.2.1 Exact Address Comparator Match (Comparators A and C)
With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the
value stored in the comparator address/data registers. Further qualification of the type of access (R/W,
word/byte) is possible.
Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. Table 6-
37 lists access considerations without data bus compare. Table 6-36 lists access considerations with data
bus comparison. To compare byte accesses DBGxDH must be loaded with the data byte, the low byte must
be masked out using the DBGxDLM mask register. On word accesses the data byte of the lower address
is mapped to DBGxDH.
Table 6-36. Comparator A and C Data Bus Considerations
Access
Word
Byte
Word
Word
Address
ADDR[n]
ADDR[n]
ADDR[n]
ADDR[n]
DBGxDH
Data[n]
Data[n]
Data[n]
x
DBGxDL
Data[n+1]
x
x
Data[n+1]
DBGxDHM
$FF
$FF
$FF
$00
DBGxDLM
$FF
$00
$00
$FF
Example Valid Match
MOVW #$WORD ADDR[n]
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
config1
config2
config2
config3
Code may contain various access forms of the same address, i.e. a word access of ADDR[n] or byte access
of ADDR[n+1] both access n+1. At a word access of ADDR[n], address ADDR[n+1] does not appear on
the address bus and so cannot cause a comparator match if the comparator contains ADDR[n]. Thus it is
not possible to monitor all data accesses of ADDR[n+1] with one comparator.
To detect an access of ADDR[n+1] through a word access of ADDR[n] the comparator can be configured
to ADDR[n], DBGxDL is loaded with the data pattern and DBGxDHM is cleared so only the data[n+1] is
compared on accesses of ADDR[n].
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
245