S912XHY128F0VLM Datasheet, PDF (77/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-2. Block Memory Map (continued)
Port
Offset or
Address
Register
Access Reset Value Section/Page
Key 0x0288 PIET—Port T Interrupt Enable Register
R/W
Wak
eup ^{0x0289 PIFT—Port T Interrupt Flag Register}
R/W
0x028A PIES—Port S Interrupt Enable Register
R/W
0x028B PIFS—Port S Interrupt Flag Register
R/W
0x028C PIE1AD—Port AD Interrupt Enable Register
R/W
0x028D PIF1AD—Port AD Interrupt Flag Register
R/W
0x028E PIER—Port R Interrupt Enable Register
R/W
0x028F PIFR—Port R Interrupt Flag Register
R/W
U 0x0290 PTU—Port U Data Register
R/W
0x0291 PTIU—Port U input Register
R
0x0292 DDRU—Port U Data Direction Register
R/W
0x0293 PIM Reserved
R
0x0294 PERU—Port U Pull Device Enable Register
R/W
0x0295 PPSU—Port U Polarity Select Register
R/W
0x0296 SRRU—Port U Slew Rate Register
R/W
0x0297 PTURR— Port S Routing Register PIM Reserved
R
V 0x0298 PTV—Port V Data Register
R/W
0x0299 PTIV—Port V Input Register
R
0x029A DDRV—Port V Data Direction Register
R/W
0x029B PIM Reserved
R
0x029C PERV—Port V Pull Device Enable Register
R/W
0x029D PPSV—Port V Polarity Select Register
R/W
0x029E SRRV—Port V Slew Rate Register
R/W
0x029F PTVRR— Port S Routing Register
R
1 _{Refer to memory map in SoC Guide to determine related module}
2 _{Write access not applicable for one or more register bits. Refer to register description}
3 _{Read always returns logic level on pins.}
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
3
0x00
0x00
0x00
0x00
0x00
0x00
0x00
3
0x00
0x00
0x00
0x00
0x00
0x00
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Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000 R
PORTA _W
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
= Unimplemented or Reserved
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
77