S912XHY128F0VLM Datasheet, PDF (95/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

2.3.16 Port T Data Direction Register (DDRT)
Port Integration Module (S12XHYPIMV1)
Address 0x0242
R
W
Reset
7
DDRT7
0
1 _{Read: Anytime}
Write: Anytime
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 2-14. Port T Data Direction Register (DDRT)
Access: User read/write¹
1
0
DDRT1
DDRT0
0
0
Table 2-13. DDRT Register Field Descriptions
Field
7-4
DDRT
Description
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding TIM0 output compare channel is enabled, it will be forced as output.
3-0
DDRT
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding TIM1 output compare channel is enabled, it will be forced as output.
1 Associated pin is configured as output
0 Associated pin is configured as input
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTT or PTIT registers, when changing the
DDRT register.
2.3.17 PIM Reserved Register
Address 0x0243
7
R
0
W
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-15. PIM Reserved Register
Freescale Semiconductor
MC9S12XHY-Family Reference Manual, Rev. 1.01
Access: User read/write¹
1
0
0
0
0
0
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