S912XHY128F0VLM Datasheet, PDF (133/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-57. WOMR Register Field Descriptions
Field
Description
7-0
WOMR
Port R wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
2.3.72 PIM Reserved Registers
Address 0x0287
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-69. PIM Reserved Registers
Access: User read¹
1
0
0
0
0
0
2.3.73 Port T Interrupt Enable Register (PIET)
Read: Anytime.
Address 0x0288
R
W
Reset
7
PIET7
0
1 _{Read: Anytime.}
Write: Anytime.
6
PIET6
5
PIET5
4
PIET4
3
PIET3
2
PIET2
0
0
0
0
0
Figure 2-70. Port TInterrupt Enable Register (PIET)
Access: User read/write¹
1
0
PIET1
PIET0
0
0
Field
7-0
PIET
Table 2-58. PIET Register Field Descriptions
Description
Port T interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port T.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
133