S912XHY128F0VLM Datasheet, PDF (127/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
1 _{Read: Anytime}
Write: Anytime
Table 2-51. PER1AD Register Field Descriptions
Field
Description
7-0 Port AD pull-up enable—Enable pull-up device on input pin
PER1AD This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
2.3.64 PIM Reserved Registers
Address 0x0278-0x27F
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-61. PIM Reserved Registers
Access: User read¹
1
0
0
0
0
0
2.3.65 Port R Data Register (PTR)
Address 0x0280
7
R
PTR7
W
6
PTR6
5
PTR5
4
PTR4
3
PTR3
2
PTR2
—
SCL
SDA
—
—
—
Altern.
Function
FP27
FP18
FP17
FP112
IOC1_7
IOC1_6
Reset
0
0
0
0
0
0
Figure 2-62. Port R Data Register (PTR)
1 _{Read: Anytime The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PTR1
PTR0
TXCAN1
IOC0_7
0
RXCAN1
IOC0_6
0
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
127