S912XHY128F0VLM Datasheet, PDF (113/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-33. DDRP Register Field Descriptions
Field
7
DDRP
Description
Port P data direction—
This register controls the data direction of pin 7.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this
pin is forced to be an input. In these cases the data direction bit will not change.
6-0
DDRP
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P data direction—
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel.
In this case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
2.3.42 PIM Reserved Registers
Address 0x025B
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-39. PIM Reserved Register
Access: User read/write¹
1
0
0
0
0
0
2.3.43 Port P Pull Device Enable Register (PERP)
Address 0x025C
R
W
Reset
7
PERP7
1
6
PERP6
5
PERP5
4
PERP4
3
PERP3
2
PERP2
1
1
1
1
1
Figure 2-40. Port P Pull Device Enable Register (PERP)
Access: User read/write¹
1
0
PERP1
PERP0
1
1
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
113