S912XHY128F0VLM Datasheet, PDF (252/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12X Debug (S12XDBGV3) Module
SUB_1
ADDR1
BRN
NOP
DBNE
*
A,PART5
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB #$F0
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
STAB VAR_C1
RTI
;
The execution flow taking into account the IRQ is as follows
LDX
#SUB_1
MARK1 JMP
0,X
;
IRQ_ISR LDAB #$F0
;
STAB VAR_C1
RTI
;
SUB_1 BRN
*
NOP
;
ADDR1 DBNE A,PART5
;
6.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
S12XDBG module writes this value into a background register. This prevents consecutive duplicate
address entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the
S12XDBG module is designed to help find.
6.4.5.2.3 Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This
mode also features information byte entries to the trace buffer, for each address byte entry. The information
byte indicates the size of access (word or byte) and the type of access (read or write).
When tracing CPU12X activity in Detail Mode, all cycles are traced except those when the CPU12X is
either in a free or opcode fetch cycle, the address range can be limited to a range specified by the TRANGE
bits in DBGTCR. This function uses comparators C and D to define an address range inside which
CPU12X activity should be traced (see Table 6-40). Thus the traced CPU12X activity can be restricted to
particular register range accesses.
6.4.5.2.4 Pure PC Mode
In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal
opcodes, are stored.
MC9S12XHY-Family Reference Manual, Rev. 1.01
252
Freescale Semiconductor