S912XHY128F0VLM Datasheet, PDF (263/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
7.3.2 Register Descriptions
This section describes in address order all the S12XECRG registers and their individual bits.
7.3.2.1 S12XECRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
VCOFRQ[1:0]
W
SYNDIV[5:0]
Reset
0
0
0
0
0
0
0
0
Figure 7-3. S12XECRG Synthesizer Register (SYNR)
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
f _VCO = 2 × f _OSC × -⁽⁽--^SR---^Y-_E---^N-_F----_DD----_I-^I--_VV------₊₊----₁-¹---₎₎-
f _PLL = ₂-----_×-----_P-^f--^VO-----^CS---_T-^O----_D----_I---_V--
f _BUS = ^f---^P---₂-^L---^L--
NOTE
f_VCO must be within the specified VCO frequency lock range. F._BUS (Bus
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
f_PLL is same as f_VCO (divide by one).
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 7-2. Setting the VCOFRQ[1:0] bits wrong can result in a non functional IPLL
(no locking and/or insufficient stability).
Table 7-2. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
32MHz <= f_VCO<= 48MHz
48MHz < f_VCO<= 80MHz
Reserved
80MHz < f_VCO <= 120MHz
VCOFRQ[1:0]
00
01
10
11
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
263